1. Field of the Invention
The present invention relates to a non-volatile memory, and in particular to a layout of a flash memory and a formation method of the same which are capable of significantly enhancing a reliability of a semiconductor apparatus by increasing a current driving capacity of a selection transistor for selecting a memory cell of a flash memory.
2. Description of the Conventional Art
Generally, in the non-volatile memory, the data stored in a cell are not erased even when a drive power is not supplied to the same. Among the non-volatile memories, the EEPROM(Electrically Erasable Programmable Read Only Memory) has a function capable of erasing the data stored in the cell at one time or by the unit of the sectors, so that it is widely used for a computer and a memory card.
This flash memory is classified into a NAND type and a NOR type in accordance with a connection state of a cell and bit line. Of which, the NOR type flash memory is formed of more than two cell transistors which are connected with one bit line in parallel, and the NAND type flash memory is formed of more than two cell transistor connected in series with one bit line.
In the large capacity flash memory, since there are many memory cells sharing a bit and word line, the stress applied to the cell which is not selected is increased. In addition, the capacitance and resistance of each bit and word line is increased, so that the structure of the cell array is generally changed as follows.
Namely, the memory cells of the large capacity flash memory are divided into a plurality of blocks for thereby decreasing the number of the shared word lines and bit lines. In this case, the memory has the advantages in that the cell characteristic is enhanced as the stress applied to the cells of the entire memories is decreased, and the operation speed of the memory is increased as the connection line between the devices is shortened.
In this case, since a peripheral circuit such as a decoder, etc. is additionally used for each divided cell block, the flash memory is connected in such a manner that the bit line is separately connected for each cell connection portion and peripheral system connection portion.
For example, one bit line is commonly used as a plurality of cell bits connecting each drain in parallel in more than two memory cells, and one array bit line connecting a memory cell to a peripheral circuit such as a bit line decoder, a page buffer, etc.
At this time, the cell bit line and array bit line are connected based on a selection transistor for driving a corresponding cell transistor among the memory cell arrays. In more detail, the array bit line is connected with a drain of the selection transistor, and the cell bit line is connected with a source of the selection transistor.
In the NOR type flash memory using the divided bit lines, when selecting a predetermined memory cell, the array bit line and memory cell are connected in a state that the selection transistor connected with a corresponding cell bit line is turned on, and the memory cell and array bit line are not connected in a state that the cell bit line connected with the non-selected memory cells and the selection transistor are turned off.
In the above-described NOR type flash memory, the stress due to the bit line may be decreased. However, since the channel width of the selection transistor is the same as the transistor of the memory cell or is smaller than the same, the channel resistance is increased, so that a RC delay problem of the bit line may occur, and the driving capacity of the circuit may be decreased.
In order to overcome the above-described problems, two transistors are integrated, and the bit line and cell bit line are provided at a ratio of 1:2, and then one array bit line is connected with two cell bit lines, respectively. Therefore, in the selection transistor, since the channel width is increased more than two times compared to the channel width of the cell transistor, the channel resistance is decreased, and the RC delay of the bit line is decreased, and the current driving capacity of the transistor is enhanced.
However, in this flash memory, since two cells among the memory cells sharing the word line co-use one array bit line, the memory cells connected with the identical word line are not programmed by one programming operation. Namely, the same are programmed by two programming operations. In addition, since the flash memory has two pages in one word line, a predetermined stress may be present in the word line. Since the sizes of one page and one section are not identical, the above-described memory is not applicable to a solid disk, thus resulting in a predetermined limit in the product specification.
Therefore, the NOR type flash memory capable of overcoming the above-described problems needs a predetermined layout proper for the design rule below a sub-micron.